The invention relates to making temporary, pressure connections between electronic components and, more particularly, to techniques for xe2x80x9cexercisingxe2x80x9d (performing test and burn-in procedures upon) semiconductor devices prior to their packaging, preferably prior to the individual semiconductor devices being singulated (separated) from a semiconductor wafer.
Individual semiconductor (intergrated circuit) devices (dies) are typically produced by creating several identical devices on a semiconductor wafer, using know techniques of photolithography, deposition, and the like. Generally, these processes are intended to create a plurality of fully-functional integrated circuit devices, prior to singulating (severing) the individual dies from the semiconductor wafer. In practice, however, certain physical defects in the wafer itself and certain defects in the processing of the wafer inevitably lead to some of the dies being xe2x80x9cgoodxe2x80x9d (fully-functional) and some of the dies being xe2x80x9cbadxe2x80x9d (non-functional). It is generally desirable to be able to identify which of the plurality of dies on a wafer are good dies prior to their packaging, and preferably prior to their being singulated from the wafer. To this end, a wafer xe2x80x9ctesterxe2x80x9d or xe2x80x9cproberxe2x80x9d may advantageously be employed to make a plurality of discrete pressure connections to a like plurality of discrete connection pads (bond pads) on the dies, and provide signals (including power) to the dies. In this manner, the semiconductor dies can be exercised (tested and burned in), prior to singulating the dies from the wafer. A conventional component of a wafer tester is a xe2x80x9cprobe cardxe2x80x9d to which a plurality of probe elements are connectedxe2x80x94tips of the probe elements effecting the pressure connections to the respective bond pads of the semiconductor dies.
Certain difficulties are inherent in any technique for probing semiconductor dies. For example, modern integrated circuits include many thousands of transistor elements requiring many hundreds of bond pads disposed in close proximity to one another (e.g., 5 mils center-to-center). Moreover, the layout of the bond pads need not be limited to single rows of bond pads disposed close to the peripheral edges of the die (See, e.g., U.S. Pat. No. 5,453,583).
To effect reliable pressure connections between the probe elements and the semiconductor die one must be concerned with several parameters including, but not limited to: alignment, probe force, overdrive, contact force, balanced contact force, scrub, contact resistance, and planarization. A general discussion of these parameters may be found in U.S. Pat. No. 4,837,622, entitled HIGH DENSITY PROBE CARD, incorporated by reference herein, which discloses a high density epoxy ring probe card including a unitary printed circuit board having a central opening adapted to receive a preformed epoxy ring array of probe elements.
Generally, prior art probe card assemblies include a plurality of tungsten needles extending as cantilevers from a surface of a probe card. The tungsten needles may be mounted in any suitable manner to the probe card, such as by the intermediary of an epoxy ring, as discussed hereinabove. Generally, in any case, the needles are wired to terminals of the probe card through the intermediary of a separate and distinct wire connecting the needles to the terminals of the probe card.
Probe cards are typically formed as circular rings, with hundreds of probe elements (needles) extending from an inner periphery of the ring (and wired to terminals of the probe card). Circuit modules, and conductive traces (lines) of preferably equal length, are associated with each of the probe elements. This ring-shape layout makes it difficult, and in some cases impossible, to probe a plurality of unsingulated semiconductor dies (multiple sites) on a wafer, especially when the bond pads of each semiconductor die are arranged in other than two linear arrays along two opposite edges of the semiconductor die. p Wafer testers may alternately employ a probe membrane having a central contact bump area, as is discussed in U.S. Pat. No. 5,422,574, entitled LARGE SCALE PROTRUSION MEMBRANE FOR SEMICONDUCTOR DEVICES UNDER TEST WITH VERY HIGH PIN COUNTS, incorporated by reference herein. As noted in this patent, xe2x80x9cA test system typically comprises a test controller for executing and controlling a series of test programs, a wafer dispensing system for mechanically handling and positioning wafers in preparation for testing and a probe card for maintaining an accurate mechanical contact with the device-under-test (DUT).xe2x80x9d (column 1, lines 41-46).
Additional references, incorporated by reference herein, as indicative of the state of the art in testing semiconductor devices, include U.S. Pat. No. 5,442,292 (TESTING AND EXERCISING INDIVIDUAL UNSINGULATED DIES ON A WAFER); U.S. Pat. No. 5,382,898 (HIGH DENSITY PROBE CARD FOR TESTING ELECTRICAL CIRCUITS); U.S. Pat. No. 5,378,982 TEST PROBE FOR PANEL HAVING AN OVERLYING PROTECTIVE MEMBER ADJACENT PANEL CONTACTS); U.S. Pat. No. 5,339,027 (RIGID-FLEX CIRCUITS WITH RAISED FEATURES AS IC TEST PROBES); U.S. Pat. No. 5,180,977 (MEMBRANE PROBE CONTACT BUMP COMPLIANCY SYSTEM); U.S. Pat. No. 5,066,907 (PROBE SYSTEM FOR DEVICE AND CIRCUIT TESTING); U.S. Pat. No. 4,757,256 (HIGH DENSITY PROBE CARD); U.S. Pat. No. 4,161,692 (PROBE DEVICE FOR INTEGRATED CIRCUIT WAFERS); and U.S. Pat. No. 3,990,689 (ADJUSTABLE HOLDER ASSEMBLY FOR POSITIONING A VACUUM CHUCK).
Generally, interconnections between electronic components can be classified into the two broad categories of xe2x80x9crelatively permanentxe2x80x9d and xe2x80x9creadily demountablexe2x80x9d.
An example of a xe2x80x9crelatively permanentxe2x80x9d connection is a solder joint. Once two components are soldered to one another, a process of unsoldering must be used to separate the components. A wire bond is another example of a xe2x80x9crelatively permanentxe2x80x9d connection.
An example of a xe2x80x9creadily demountablexe2x80x9d connection is rigid pins of one electronic component being received by resilient socket elements of another electronic component. The socket element exert a contact force (pressure) on the pins in an amount sufficient to ensure a reliable electrical connection therebetween.
Interconnection elements intended to make pressure contact with terminals of an electronic component are referred to herein as xe2x80x9cspringsxe2x80x9d or xe2x80x9cspring elementsxe2x80x9d. Generally, a certain minimum contact force is desired to effect reliable pressure contact to electronic components (e.g., to terminals on electronic components). For example, a contact (load) force of approximately 15 grams (including as little as 2 grams or less and as much as 150 grams or more, per contact) may be desired to ensure that a reliable electrical connection is made to a terminal of an electronic component which may be contaminated with films on its surface, or which has corrosion or oxidation products on its surface. The minimum contact force required of each spring demands either that the yield strength of the spring material or that the size of the spring element are increased. As a general proposition, the higher the yield strength of a material, the more difficult it will be to work with (e.g., punch, bend, etc.). And the desire to make springs smaller essentially rules out making them larger in cross-section.
Probe elements are a class of spring elements of particular relevance to the present invention. Prior art probe elements are commonly fabricated from titanium, a relatively hard (high yield strength) material. When it is desired to mount such relatively hard materials to terminals of an electronic component, relatively xe2x80x9chostilexe2x80x9d (e.g., high temperature) processes such as brazing are required. Such xe2x80x9chostilexe2x80x9d processes are generally not desirable (and often not feasible) in the context of certain relatively xe2x80x9cfragilexe2x80x9d electronic components such as semiconductor devices. In contrast thereto, wire bonding is an example of a relatively xe2x80x9cfriendlyxe2x80x9d processes which is much less potentially damaging to fragile electronic components than brazing. Soldering is another example of a relatively xe2x80x9cfriendlyxe2x80x9d process. However, both solder and gold are relatively soft (low yield strength) materials which will not function well as spring elements.
A subtle problem associated with interconnection elements, including spring contacts, is that, often, the terminals of an electronic component are not perfectly coplanar. Interconnection elements lacking in some mechanism incorporated therewith for accommodating these xe2x80x9ctolerancesxe2x80x9d (gross non-planarities) will be hard pressed to make consistent contact pressure contact with the terminals of the electronic component.
The following U.S. Pat. Nos., incorporated by reference herein, are cited as being of general interest vis-a-vis making connections, particularly pressure connections, to electronic components: U.S. Pat. No. 5,386,344 (FLEX CIRCUIT CARD ELASTOMERIC CABLE CONNECTOR ASSEMBLY); U.S. Pat. No. 5,336,380 (SPRING BIASED TAPERED CONTACT ELEMENTS FOR ELECTRICAL CONNECTORS AND INTEGRATED CIRCUIT PACKAGES); U.S. Pat. No. 5,317,479 (PLATED COMPLIANT LEAD); U.S. Pat. No. 5,086,337 (CONNECTING STRUCTURE OF ELECTRONIC PART AND ELECTRONIC DEVICE USING THE STRUCTURE); U.S. Pat. No. 5,067,007 (SEMICONDUCTOR DEVICE HAVING LEADS FOR MOUNTING TO A SURFACE OF A PRINTED CIRCUIT BOARD); U.S. Pat. No. 4,989,069 (SEMICONDUCTOR PACKAGE HAVING LEADS THAT BREAK-AWAY FROM SUPPORTS); U.S. Pat. No. 4,893,172 (CONNECTING STRUCTURE FOR ELECTRONIC PART AND METHOD OF MANUFACTURING THE SAME); U.S. Pat. No. 4,793,814 (ELECTRICAL CIRCUIT BOARD INTERCONNECT); U.S. Pat. No. 4,777,564 (LEAD FOR USE WITH SURFACE MOUNTED COMPONENTS); U.S. Pat. No. 4,764,848 (SURFACE MOUNTED ARRAY STRAIN RELIEF DEVICE); U.S. Pat. No. 4,667,219 (SEMICONDUCTOR CHIP INTERFACE); U.S. Pat. No. 4,642,889 (COMPLAINT INTERCONNECTION AND METHOD THEREFOR); U.S. Pat. No. 4,330,165 (PRESS-CONTACT TYPE INTERCONNECTORS); U.S. Pat. No. 4,295,700 (INTERCONNECTORS); U.S. Pat. No. 4,067,104 (METHOD OF FABRICATING AN ARRAY OF FLEXIBLE METALLIC INTERCONNECTS FOR COUPLING MICROELECTRONICS COMPONENTS); U.S. Pat. No. 3,795,037 (ELECTRICAL CONNECTOR DEVICES); U.S. Pat. No. 3,616,532 (MULTILAYER PRINTED CIRCUIT ELECTRICAL INTERCONNECTION DEVICE); and U.S. Pat. No. 3,509,270 (INTERCONNECTION FOR PRINTED CIRCUITS AND METHOD OF MAKING SAME).
Generally, throughout the probe techniques described hereinabove, a probe card or the like having a plurality of resilient contact structures extending from or upon a surface thereof is urged against a semiconductor wafer to make pressure contacts with a corresponding plurality of terminals (bond pads) on an individual semiconductor die. In some cases, pressure contact with a limited number (e.g., four) of unsingulated dies arranged end-to-end can be made, depending upon the layout of the bond pads on the semiconductor dies (e.g., a linear array of bond pads on each of the two side edges of the dies). (The end-to-end dies can be treated as one long die having two rows of bond pads).
A limited number of techniques are suggested in the prior art for providing semiconductor chip assemblies with terminals that are biased away from the surface of the semiconductor die (chip). U.S. Pat. No. 5,414,298, entitled SEMICONDUCTOR CHIP ASSEMBLIES AND COMPONENTS WITH PRESSURE CONTACT, discloses that such an assembly xe2x80x9ccan be extremely compact and may occupy an area only slightly larger than the area of the chip itself.xe2x80x9d
One might be tempted to surmise that it is a simple intuitive step to expand such techniques to wafer-level. To the contrary, it is not at all apparent how such xe2x80x9cassembliesxe2x80x9d which are larger than the die could be accommodated at wafer-level, without requiring there to be a greatly expanded kerf (scribing) area disposed between each adjacent die. Additionally, it is not at all apparent how such xe2x80x9cassembliesxe2x80x9d would be fabricated upon a plurality of unsingulated dies. Moreover, such assemblies are generally constrained to xe2x80x9ctranslatingxe2x80x9d peripheral arrays (i.e., a peripheral (edge) layout of bond pads on a semiconductor die) to area arrays (e.g., rows and columns) of terminals, and require a good deal of valuable xe2x80x9creal estatexe2x80x9d to effect the translation. Routing the connections is one serious limitation, and typically the connections xe2x80x9cfan-inxe2x80x9d. The use of non-metallic materials (i.e., materials incapable of sustaining high temperatures) is another concern.
Another serious concern with any technique such as is described in the aforementioned U.S. Pat. No. 5,414,298 is that the face of the die is covered. This is generally undesirable, and is particularly undesirable in the context of gallium arsenide (GaAs) semiconductor devices.
It is an object of the present invention to provide a technique for testing (exercising and/or burning-in) semiconductor dies, prior to their being singulated (separated) from a semiconductor wafer.
It is another object of the present invention to provide a technique for probing semiconductor dies, prior to their being singulated (separated) from a semiconductor wafer, without being constrained by the arrangement of dies or the layout of bond pads on the dies.
It is another object of the present invention to provide a technique for probing semiconductor dies, prior to their being singulated (separated) from a semiconductor wafer, with the requisite resiliency and/or compliance being resident on the semiconductor dies, rather than requiring the probe cards to be provided with resilient contact structures extending therefrom.
It is another object of the invention to mount resilient contact structures directly to semiconductor devices, thereby permitting exercising (testing and burning-in) the devices via the resilient contact structures, and using the same resilient contact structures for final packaging of the semiconductor devices.
It is another object of the present invention to provide a technique for satisfactorily burning-in semiconductor devices in several minutes (versus several hours).
It is another object of the present invention to provide an improved spring element (resilient contact structure) that can be mounted directly to a terminal of an electronic component.
It is another object of the invention to provide interconnection elements that are suitable for making pressure contact to electronic components.
According to the invention, spring contact elements (composite interconnection elements) are mounted directly to semiconductor dies. Preferably, the spring contact elements are mounted to the semiconductor dies prior to the semiconductor dies being singulated (separated) from a semiconductor wafer. In this manner, a plurality of pressure contacts can be made to one or more unsingulated semiconductor dies (devices) using a xe2x80x9csimplexe2x80x9d test board to power-up the semiconductor devices, and the like.
As used herein, a xe2x80x9csimplexe2x80x9d test board is a substrate having a plurality of terminals, or electrodes, as contrasted with a traditional xe2x80x9cprobe cardxe2x80x9d which is a substrate having a plurality of probe elements extending from a surface thereof. A simple test board is less expensive, and more readily configured than a traditional probe card. Moreover, certain physical constraints inherent in traditional probe cards are not encountered when using a simple test board to make the desired pressure contacts with semiconductor devices.
In this manner, a plurality of unsingulated semiconductor dies can be exercised (tested and/or burned in) prior to the semiconductor dies being singulated (separated) from the wafer.
According to an aspect of the invention, the same spring contact elements which are mounted to the semiconductor dies and which are used to exercise the semiconductor dies can be used to make permanent connections to the semiconductor dies after they have been singulated from the wafer.
According to an aspect of the invention, the resilient contact structures are preferably formed as xe2x80x9ccomposite interconnection elementsxe2x80x9d which are fabricated directly upon the terminals of the semiconductor device. The xe2x80x9ccompositexe2x80x9d (multilayer) interconnection element is fabricated by mounting an elongate element (xe2x80x9ccorexe2x80x9d) to an electronic component, shaping the core to have a spring shape, and overcoating the core to enhance the physical (e.g., spring) characteristics of the resulting composite interconnection element and/or to securely anchor the resulting composite interconnection element to the electronic component. The resilient contact structures of the interpose component may also be formed as composite interconnection elements.
The use of xe2x80x9ccompositexe2x80x9d, throughout the description set forth herein, is consistent with a xe2x80x98genericxe2x80x99 meaning of the term (e.g., formed of two or more elements), and is not to be confused with any usage of the term xe2x80x9ccompositexe2x80x9d in other fields of endeavor, for example, as it may be applied to materials such as glass, carbon or other fibers supported in a matrix of resin or the like.
As used herein, the term xe2x80x9cspring shapexe2x80x9d refers to virtually any shape of an elongate element which will exhibit elastic (restorative) movement of an end (tip) of the elongate element with respect to a force applied to the tip. This includes elongate elements shaped to have one or more bends, as well as substantially straight elongate elements.
As used herein, the terms xe2x80x9ccontact areaxe2x80x9d, xe2x80x9cterminalxe2x80x9d, xe2x80x9cpadxe2x80x9d, and the like refer to any conductive area on any electronic component to which an interconnection element is mounted or makes contact.
Alternatively, the core is shaped prior to mounting to an electronic component.
Alternatively, the core is mounted to or is a part of a sacrificial substrate which is not an electronic component. The sacrificial substrate is removed after shaping, and either before or after overcoating. According to an aspect of the invention, tips having various topographies can be disposed at the contact ends of the interconnection elements. (See also FIGS. 11A-11F of the PARENT CASE).
In an embodiment of the invention, the core is a xe2x80x9csoftxe2x80x9d material having a relatively low yield strength, and is overcoated with a xe2x80x9chardxe2x80x9d material having a relatively high yield strength. For example, a soft material such as a gold wire is attached (e.g., by wire bonding) to a bond pad of a semiconductor device and is overcoated (e.g., by electrochemical plating) with a hard material such nickel and its alloys.
Vis-a-vis overcoating the core, single and multi-layer overcoatings, xe2x80x9croughxe2x80x9d overcoatings having microprotrusions (see also FIGS. 5C and 5D of the PARENT CASE), and overcoatings extending the entire length of or only a portion of the length of the core, are described. In the latter case, the tip of the core may suitably be exposed for making contact to an electronic component (see also FIG. 5B of the PARENT CASE).
Generally, throughout the description set forth herein, the term xe2x80x9cplatingxe2x80x9d is used as exemplary of a number of techniques for overcoating the core. It is within the scope of this invention that the core can be overcoated by any suitable technique including, but not limited to: various processes involving deposition of materials out of aqueous solutions; electrolytic plating; electroless plating; chemical vapor deposition (CVD); physical vapor deposition (PVD); processes causing the deposition of materials through induced disintegration of liquid or solid precursors; and the like, all of these techniques for depositing materials being generally well known.
Generally, for overcoating the core with a metallic material such as nickel, electrochemical processes are preferred, especially electroless plating.
In another embodiment of the invention, the core is an elongate element of a xe2x80x9chardxe2x80x9d material, inherently suitable to functioning as a spring element, and is mounted at one end to a terminal of an electronic component. The core, and at least an adjacent area of the terminal, is overcoated with a material which will enhance anchoring the core to the terminal. In this manner, it is not necessary that the core be well-mounted to the terminal prior to overcoating, and processes which are less potentially damaging to the electronic component may be employed to xe2x80x9ctackxe2x80x9d the core in place for subsequent overcoating. These xe2x80x9cfriendlyxe2x80x9d processes include soldering, gluing, and piercing an end of the hard core into a soft portion of the terminal.
Preferably, the core is in the form of a wire. Alternatively, the core is a flat tab (conductive metallic ribbon).
Representative materials, both for the core and for the overcoatings, are disclosed.
In the main hereinafter, techniques involving beginning with a relatively soft (low yield strength) core, which is generally of very small dimension (e.g., 3.0 mil or less) are described. Soft materials, such as gold, which attach easily to semiconductor devices, generally lack sufficient resiliency to function as springs. (Such soft, metallic materials exhibit primarily plastic, rather than elastic deformation). Other soft materials which may attach easily to semiconductor devices and posses appropriate resiliency are often electrically non-conductive, as in the case of most elastomeric materials. In either case, desired structural and electrical characteristics can be imparted to the resulting composite interconnection element by the overcoating applied over the core. The resulting composite interconnection element can be made very small, yet can exhibit appropriate contact forces. Moreover, a plurality of such composite interconnection elements can be arranged at a fine pitch (e.g., 10 mils), even though they have a length (e.g., 100 mils) which is much greater than the distance to a neighboring composite interconnection element (the distance between neighboring interconnection elements being termed xe2x80x9cpitchxe2x80x9d).
It is within the scope of this invention that composite interconnection elements can be fabricated on a microminiature scale, for example as xe2x80x9cmicrospringsxe2x80x9d for connectors and sockets, having cross-sectional dimensions on the order of twenty-five microns (xcexcm), or less. This ability to manufacture reliable interconnection having dimensions measured in microns, rather than mils, squarely addresses the evolving needs of existing interconnection technology and furture area array technology.
The composite interconnection elements of the present invention exhibit superior electrical characteristics, including electrical conductivity, solderability and low contact resistance. In many cases, deflection of the interconnection element in response to applied contact forces results in a xe2x80x9cwipingxe2x80x9d contact, which helps ensure that a reliable contact is made.
Ad additional advantage of the present invention is that connections made with the interconnection elements of the present invention are readily demountable. Soldering, to effect the interconnection to a terminal of an electronic component is optional, but is generally not preferred at a system level.
According to an aspect of the invention, techniques are described for making interconnection elements having controlled impedance. These techniques generally involve coating (e.g., electrophoretically) a conductive core or an entire composite interconnection element with a dielectric material (insulating layer), and overcoating the dielectric material with an outer layer of a conductive material. By grounding the outer conductive material layer, the resulting interconnection element can effectively be shielded, and its impedance can readily be controlled. (See also FIG. 10K of the PARENT CASE).
According to an aspect of the invention, interconnection elements can be pre-fabricated as individual units, for later attachment to electronic components. Various techniques for accomplishing this objective are set forth herein. Although not specifically covered in this document, it is deemed to be relatively straightforward to fabricate a machine that will handle the mounting of a plurality of individual interconnection elements to a substrate or, alternatively, suspending a plurality of individual interconnection elements in an elastomer, or on a support substrate.
It should clearly be understood that the composite interconnection element of the present invention differs dramatically from interconnection elements of the prior art which have been coated to enhance their electrical conductivity characteristics or to enhance their resistance to corrosion.
The overcoating of the present invention is specifically intended to substantially enhance anchoring of the interconnection element to a terminal of an electronic component and/or to impart desired resilient characteristics to the resulting composite interconnection element. Stresses (contact forces) are directed to portions of the interconnection elements which are specifically intended to absorb the stresses.
It should also be appreciated that the present invention provides essentially a new technique for making spring structures. Generally, the operative structure of the resulting spring is a product of plating, rather than of bending and shaping. This opens the door to using a wide variety of materials to establish the spring shape, and a variety of xe2x80x9cfriendlyxe2x80x9d processes for attaching the xe2x80x9cfalseworkxe2x80x9d of the core to electronic components. The overcoating functions as a xe2x80x9csuperstructurexe2x80x9d over the xe2x80x9cfalseworkxe2x80x9d of the core, both of which terms have their origins in the field of civil engineering.
A distinct advantage of the present invention is that probe elements (resilient contact structures) can be fabricated directly on terminal of a semiconductor device without requiring additional materials, such as brazing or soldering.
According to an aspect of the invention, any of the resilient contact structures may be formed as at least two composite interconnection elements.
Among the benefits of the present invention are:
(a) the composite interconnection elements are all metallic, permitting burn-in to be performed at elevated temperatures and, consequently, in a shorter time.
(b) the composite interconnection elements are free-standing, and are generally not limited by the bond pad layout of semiconductor devices.
(c) the composite interconnection elements of the present invention can be fashioned to have their tips at a greater pitch (spacing) than their bases, thereby immediately (e.g., at the first level interconnect) commencing and facilitating the process of spreading pitch from semiconductor pitch (e.g., 10 mils) to wiring substrate pitch (e.g., 100 mils).
Other objects, features and advantages of the invention will become apparent in light of the following description thereof.